1. Field of the Invention
The present invention generally relates to a semiconductor device. More specifically, the present invention is directed to a semiconductor device having an element isolating region provided with a trench and an insulating film embedded in the trench, and a manufacturing method thereof.
2. Description of the Related Art
In MOS transistors, while insulating films which constitute side walls are formed on side walls of gate electrodes of these MOS transistors, impurities are implanted in both ends of the insulating films so as to form source regions and drain regions. There are many cases in which crystalline defects may occur in silicon substrates at edge portions of the source regions and drain regions of MOS transistors. As one such method that is capable of preventing the above-described crystalline defects, JP-A-08-97210 (patent publication No. 1) discloses a semiconductor device structure, as indicated in FIG. 8, in which the oxide film is interposed between the side surface of the gate electrode, the silicon nitride film which constitutes the side wall, and the substrate under this silicon nitride film.
Also, nonvolatile semiconductor memory devices capable of electrically writing/erasing data can be easily used, for instance, data are rewritable under such a condition that these nonvolatile semiconductor memory devices are assembled on wiring boards. As a result, these nonvolatile semiconductor memory devices have been widely utilized in various sorts of products which require memories.
More specifically, electrically erasable programmable read-only memories (EEPROM, will be also referred to as “flash memories” hereinafter) own such a function capable of electrically erasing data of a predetermined range (e.g., all memory cells of a memory array, or a predetermined memory cell group of a memory array) within a memory array in a batch manner. Furthermore, since flash memories may have 1-transistor stacked layer gate structures, memory cells thereof may be gradually made compact and, therefore, higher levels of integration of these memory cells may be greatly expected.
A 1-transistor stacked layer gate structure, constituting one nonvolatile memory cell (will be abbreviated as “memory cell” hereinafter), is basically formed of one two-layer gate metal-insulator-silicon field-effect transistor (will be abbreviated as “MISFET” hereinafter). This two-layer gate MISFET is formed in such a way that a floating gate electrode is formed via a tunnel insulating film on a semiconductor substrate, and, further, a control gate electrode is stacked via an interlayer film on this formed floating gate electrode. A data storing operation is carried out in which electrons are injected into the floating gate electrode and electrons are extracted from the floating gate electrode.
As to flash memories, both a parallel type flash memory having such a memory array structure, and a method of using this parallel type flash memory are disclosed in, for example, JP-A-08-97210. This parallel type flash memory is constructed by containing a plurality of memory cells which are arranged in a matrix shape on a semiconductor substrate in such a manner that source/drain regions of the above-explained plural memory cells are parallel connected to each other in the respective rows of this matrix, and word lines are elongated in the respective columns of this matrix. This sort of flash memory is also referred to as an “AND type flash memory.”
However, the Inventors of the present invention have found that the memory structures of the above-described prior art cannot sufficiently suppress crystalline defects which occur in substrates of active regions containing source regions, drain regions, and the like. The reason for this is given as follows: the occurrences of the crystalline defects not only result from stresses of gate electrodes, but also stresses produced from element isolating regions as well as factors caused by implanted impurities, which may have unduly large influences.
The Inventors of the present invention have also found the below-mentioned problems in the development of semiconductor integrated circuit devices having the above-described AND type configured flash memories. Namely, since flash memories are being manufactured with higher levels of integration, memory cells are correspondingly made very fine. At the same time, occurrence of crystalline defects in substrates have correspondingly increased. Therefore, such has been determined that junction leaks in the memory cells may occur many times, so that data reading failures may occur in these memory cells, or data destroy modes may occur.
This crystalline defect may be caused by, for instance, stresses produced in regions into which impurity ions have been implanted, and stresses produced in the forming steps of either gate electrodes or element isolating portions. More specifically, in such a case that an element isolating portion is constructed of a shallow trench isolation (Shallow Trench Isolation; will be referred to as “STI” hereinafter), such a fact could be seen that a large number of crystalline defects are produced in a substrate.
An STI is formed in such a manner that, for example, after a shallow trench has been formed in a substrate, an insulating film is embedded inside this trench and a surface of this embedded insulating film is, furthermore, flattened (i.e., planarized). However, at a thermal processing step higher than, or equal to 800° C., which is executed after the STI has been formed, a volume expansion may occur which is caused by the growth of an oxide film on a side wall of the trench, and this volume expansion is restricted by the insulating film embedded inside the trench, so that compression stresses are produced in the substrate, which may cause the occurrences of the crystalline defects.
This compression stress may be easily concentrated to such a place that a width of an active region is relatively narrow and also pattern density is relatively high. As a consequence, in a flash memory, a large number of crystalline detects may occur in such a region that a width of an active region is relatively wide, for instance, in a memory array where a width of an active region is relatively narrower than that of a peripheral circuit region, which may conduct junction leaks of a memory cell.